1. Technical Field
The present invention relates to network interfaces, and more specifically to arrangements in network interfaces for transferring data using Direct Memory Access (DMA) techniques via a host bus between a host memory and the network interface.
2. Description of Related Art
Network interfaces connecting a host computer to a network such as an Ethernet-type or IEEE 802.3 network, typically utilize a host bus to transfer information between a host memory and the network interface. Two types of bus transfers may be used, namely master mode and slave mode. In master mode, a transaction or transfer of information over the bus is initiated by a master, which arbitrates for use of the bus along with other masters requesting use of the bus.
One example of a host bus is the peripheral component interconnect (PCI) local bus. A single transaction or transfer of information over a PCI bus comprises an address phase followed by one or more contiguous data phases. In conducting transactions, the PCI bus makes use of a centralized, synchronous arbitration scheme in which each PCI master arbitrates for each transaction using a unique request and grant signal. These signal lines are attached to a central arbiter and a request-grant handshake is used to grant the master access to the bus. A common sequence for a request-grant handshake is begun when the master asserts a request signal to request use of the bus. A host CPU will respond with a grant signal, followed by assertion of a frame signal that in combination identify to the network interface when the bus is available for data transfers.
The period of time between the assertion of the request signal and the grant signal is known as arbitration latency. The arbitration latency may delay transfer of data by the network interface on the host bus, and is based on the arbitration algorithm used by the host CPU, the relative priority compared to other devices accessing the bus, and system utilization. Since the PCI bus specification does not dictate a particular arbitration algorithm, arbitration latency is variable. Prior art approaches to arbitration simply wait until the frame signal is asserted before transferring data to a target via the host bus. Since the arbitration latency is a function of the arbitration algorithm, this approach causes unnecessary arbitration delays which causes additional wait states to be experienced during the transfer.